1. Field of the Invention
Embodiments of the present invention generally relate to wafer probe cards for testing semiconductor devices and, more specifically, to enhancing the performance of wafer probe cards.
2. Description of the Related Art
Testing is an important step in the production of semiconductor devices for use. Typically, partially or fully completed semiconductor devices are tested by bringing terminals disposed on an upper surface of a device to be tested—also referred to as a device under test (or DUT)—into contact with resilient contact elements, for example, as contained in a probe card assembly, as part of a test system. A test system controller with increased test channels can be a significant cost factor for a test system. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel. Unfortunately, the number of DUTs per wafer has typically outpaced the development of test system controllers. Conventionally, available channels are typically inadequate for testing all DUTs on a wafer at the same time.
One technique to accommodate testing of components on a wafer with a limited number of test channels is to fan out a signal from a test system controller in the probe card assembly to multiple transmission lines. That is, a test signal normally provided to a single DUT can be fanned out to multiple DUTs in the probe card assembly. This technique can enable testing of an increased number of DUTs during a single touchdown for a fixed number of test system channels.
To better assure test integrity with fan out, increased circuitry can be provided on the probe card assembly to minimize the effect of a fault on one of the fan out lines (e.g., a short to ground through the DUT). A fault in a component connected on a fanned out line can severely attenuate a test signal for all DUTs on the fanned out test system channel. One solution involves the use of relays between the channel line branch points and probes to reduce attenuation caused by the faulty component. Each relay requires at least one separate line for controlling its state. A probe card assembly, however, may include several thousands of such branch points, requiring several thousands of relays. Including several thousands of control lines for controlling the relays on the probe card assembly is undesirable in terms of the required area and in terms of cost.
Accordingly, there exists a need in the art for a method and apparatus for testing semiconductor devices that attempts to overcome at least the aforementioned deficiencies.